The Inter-Integrated Circuit serial bus, which may also be referred to as the I2C bus or the I2C bus, is a serial single-ended computer bus that was intended for use in connecting low-speed peripherals to a processor. The I2C bus is a multi-master bus in which each device can serve as a master and a slave for different messages transmitted on the I2C bus. The I2C bus can transmit data using only two bidirectional open-drain connectors, including a Serial Data Line (SDA) and a Serial Clock Line (SCL). The connectors typically include signal wires that are terminated by pull-up resistors.
Protocols governing I2C bus operations define basic types of messages, each of which begins with a START and ends with a STOP. The I2C bus uses 7-bit addressing and defines two types of nodes. A master node is a node that generates the clock and initiates communication with slave nodes. A slave node is a node that receives the clock and responds when addressed by the master. The I2C bus is a multi-master bus, which means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (i.e., after a STOP is sent).
Traditional I2C systems use separate interrupt request (IRQ) lines for each slave device, which increases master device cost due to the large number of pins. These IRQ lines allow a slave device to request the attention of a master device and/or to indicate to the master device when it wishes to communicate over a data bus.
Therefore, a way is needed to reduce the number or IRQ lines coming into a master device from a plurality of slave devices.